View MB89951_3114540.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds07-12529-1e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89950 series MB89951/953/p955/pv950 n outline the mb89950 series of single-chip compact microcontroller using the f 2 mc*-8l family core which can operate at high-speeds and low voltages. they contain peripherals such as timers, uart, serial interfaces, external interrupts and a 168-pixel lcd controller/driver. it is best suited for use in lcd panels. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? minimum instruction execution time: 0.8 m s at 5 mhz ?f 2 mc-8l family cpu core (continued) n pac k ag e multiplication and division instructions 16-bit arithmetic operation instruction test and branch instruction bit manipulation instruction, etc. instruction system most suited to controllers 64-pin plastic qfp (fpt-64p-m09) 64-pin ceramic mqfp (mqp-64c-p01)
mb89950 series 2 (continued) ? lcd controller/driver maximum 42 segment outputs x 4 common outputs build-in lcd driver split resistor ? three-channel timer unit 8-bit pwm timer: (usable as both reload timer and pwm timer) 8-bit pulse width counter timer: (usable as both reload timer) 20-bit timebased counter ? two serial interfaces 8-bit synchronous serial interface uart (5, 7, and 8-bit transfers possible) ? external-interrupt input: 2 channels 2 channels can be used to clear the low-power consumption modes an edge detection function is provided for each channel ? low-power consumption modes stop mode (oscillation stops to minimize the current consumption) sleep mode (cpu stops to reduce current consumption to about 30%) ? package: qfp-64 (0.65mm pitch)
mb89950 series 3 n product lineup *1: mask option. *2: varies with conditions such as the operating frequency. (see n electrical characteristics.) mb89953 mb89p955 mb89pv950 classification mass-produced products (mask rom product) one-time prom products piggyback/ evaluation and development ptoduct rom size 4 k 8 bits (internal mask rom) 8 k 8 bits (internal mask rom) 16 k 8 bits (internal prom, to be programmed with general-purpose eprom programmer) 32 k 8 bits (external rom) ram size 128 8 bits 256 8 bits 512 8 bits 1024 8 bits cpu functions the number of basic instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum imstruction execution time: 0.8 m s at 5 mhz (v cc =5.0 v) interrupt processing time: 7.2 m s at 5 mhz (v cc =5.0 v) por ts i/o port (n-ch open-drain): 22 (also used as segment pin)* 1 i/o port (n-ch open-drain): 4 (two of them are also used as lcd bias pins) i/o port (cmos): 7 (6 used as peripheral) total: 33 (max.) 8-bit pwm timer 8-bit reload timer operation (toggle output possible) 8-bit resolution pwm operation operation clock (pulse-width count timer output: 0.8 m s, 12.8 m s, 51.2 m s/5 mhz) 8-bit pulse-width counter timer 8-bit reload timer operation 8-bit pulse width measurement (continuous measurement, high- and low-width measurement, and one-cycle measurement) operation clock (0.8 m s, 3.2 ms, 25.6 m s/5 mhz) 8-bit serial i/o 8-bit length, selectable from least significant bit (lsb) first or most significant bit (msb) first, transfer clock (external, 1.6 m s, 6.4 ms, 25.6 m s/5 mhz) uart 5-, 7-, 8-bit transfers possible, internal baud-rate generator (max. 78125 bps/5 mhz) lcd controller/ driver common output: 4 segment output: 42 (max.) operation mode: 1/2 bias and 1/2 duty, 1/3 bias and 1/3 duty, 1/3 bias and 1/4 duty lcd controller display ram capacity: 42 4 bits lcd driver split resistor: built-in (external resistor selectable) external interrupt 2 (edge selectable: one serving as pulse-width count timer input) standby mode sl eep mode, stop mode power supply voltage* 2 2.2 v to 6.0 v 2.7 v to 6.0 v eprom mbm27c256a-20tv (lcc package) MB89951 part number item
mb89950 series 4 n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. package MB89951 mb89953 mb89p955 mb89pv950 fpt-64p-m09 mqp-64c-p01
mb89950 series 5 n pin assignment p00/seg20 p01/seg21 p02/seg22 p03/seg23 p04/seg24 p05/seg25 p06/seg26 p07/seg27 p10/seg28 p11/seg29 p12/seg30 p13/seg31 p14/seg32 p15/seg33 p16/seg34 p17/seg35 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 v cc seg13 seg14 seg15 seg16 seg17 seg18 seg19 p42/int1/pwc p43/si rst p44/so moda x0 x1 v ss p45/sck p46/int0 p25/seg41 p24/seg40 p23/seg39 p22/seg38 p21/seg37 p20/seg36 seg4 seg3 seg2 seg1 seg0 com3 com2 com1 com0 v3 p33/v2 p32/v1 p31 p30 p40 p41/pwm 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (top view) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (fpt-64p-m09)
mb89950 series 6 ? pin assignment on package top (mb89pv950 only) n.c.:internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65 n.c. 73 a2 81 n.c. 89 oe 66 v pp 74 a1 82 o4 90 n.c. 67a1275a083o591a11 68 a7 76 n.c. 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88 a10 96 v cc seg5 seg4 seg3 seg2 seg1 seg0 com3 com2 com1 com0 v3 p33/v2 p32/v1 p31 p30 p40 p41/pwm p42/int1/pwc p43/si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 seg18 seg19 p00/seg20 p01/seg21 p02/seg22 p03/seg23 p04/seg24 p05/seg25 p06/seg26 p07/seg27 p10/seg28 p11/seg29 p12/seg30 p13/seg31 p14/seg32 p15/seg33 p16/seg34 p17/seg35 p20/seg36 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 rst p44/so moda x0 x1 vss p45/sck p46/int0 p25/seg41 p24/seg40 p23/seg39 p22/seg38 p21/seg37 64 63 62 61 60 59 58 57 56 55 54 53 52 seg6 seg7 seg8 seg9 seg10 seg11 seg12 vcc seg13 seg14 seg15 seg16 seg17 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 94 95 96 65 66 67 68 84 83 82 81 80 79 78 (top view) (mqp-64c-p01)
mb89950 series 7 n pin description (continued) *1: fpt-64p-m09 *2: mqp-64c-p01 pin no. pin name circuit type function qfp *1 mqfp *2 22 23 x0 a clock oscillator pins 23 24 x1 21 22 moda b operation-mode select pin this pin is connected directly to v ss with pull down resistor. 19 20 rst c reset i/o pin this pin consists of an n-ch open-drain output with a pull-up resistor and hysteresis input. a low level is put out from this pin. a low voltage on this port generates a reset condition 48 to 41 49 to 42 p00/seg20 to p07/seg27 d n-channel open-drain type general-purpose i/o ports also serve as lcdc controller segment outputs. switching between port output and segment output is performed by the mask option every 8 bits. 40 to 33 41 to 34 p10/seg28 to p17/seg35 d n-channel open-drain type general-purpose i/o ports also serve as lcdc controller segment outputs. switching between port output and segment output is performed by the mask option. 32 to 27 33 to 28 p20/seg36 to p25/seg41 d n-channel open-drain type general-purpose i/o ports also serve as lcdc controller segment outputs. switching between port output and segment output is performed by the mask option. 14 to 11 15 to 12 p30 to p31 f n-channel open-drain type general-purpose i/o ports 12 to 11 13 to 12 p32/v1 to p33/v2 d n-channel open-drain type general-purpose i/o ports also serve as lcdc controller power supply. 15 16 p40 e general-purpose i/o port a pull-up resistor option is provided. 16 17 p41/pwm e general-purpose i/o port serves as pwm timer toggle output (pwm). a pull-up resistor option is provided. 17 18 p42/pwc/int1 e general-purpose i/o port also serves as pulse-width count timer input (pwc) and external interrupt input (int1) the pwc and int1 inputs are of a hysteresis type. a pull-up resistor option is provided. 18 19 p43/si e general-purpose i/o port also serves as serial i/o and uart data input (si) the si input is of a hysteresis type. a pull-up resistor option is provided. 20 21 p44/so e general-purpose i/o port also serves as serial i/o and uart data output (so). a pull-up resistor option is provided.
mb89950 series 8 (continued) *1: fpt-64p-m09 *2: mqp-64c-p01 pin no. pin name circuit type function qfp *1 mqfp *2 25 26 p45/sck e general-purpose i/o port also serves as serial i/o and uart clock input/output (sck). the sck input is of a hysteresis type. a pull-up resistor option is provided. 26 27 p46/int0 e general-purpose input port also serves as external-interrupt input (int0). the input is of a hysteresis type. a pull-up resistor option is provided. 5 to 1, 64 to 57, 55 to 49 6 to 1, 64 to 58, 56 to 50 seg0 to seg4, seg5 to seg12, seg13 to seg19 g for lcdc controller segment ouput 9 to 6 7 to 10 com0 to com3 g for lcdc controller common output 10 11 v3 for lcd driver power supply 56 57 v cc power supply pin 24 25 v ss power supply (gnd) pin
mb89950 series 9 external eprom pins (mb89pv950 only) pin no. pin name i/o function 66 v pp o h level output pin 67 68 69 70 71 72 73 74 75 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 77 78 79 o1 o2 o3 i data input pins 80 v ss o power supply (gnd) pins 82 83 84 85 86 o4 o5 o6 o7 o8 i data input pins 87 ce o rom chip enable pin outputs h during standby. 88 a10 o address output pin 89 oe o rom output enable pin outputs l at all times. 91 92 93 94 95 a11 a9 a8 a13 a14 o address output pins 96 v cc o eprom power supply pin 65 76 81 90 n.c. internally connected pins be sure to leave them open.
mb89950 series 10 n i/o circuit type (continued) type circuit remarks a ? crystal oscillator ? feedback resistor: approx. 1 m w /5.0 v (1 to 5 mhz) b ? cmos input ? pull-down resistor (n-ch) c ? output pull-up resistor (p-ch): approx. 50 k w (5.0 v) ? hysteresis input d ? n-ch open-drain output ? cmos input ? the segment output is optional. e ? cmos output ? cmos input ? hysteresis input (peripheral input) ? the pull-up resistor is optional. x1 n-ch n-ch n-ch p-ch p-ch x0 standby control signal r n-ch p-ch r n-ch n-ch n-ch p-ch p-ch n-ch p-ch p-ch r
mb89950 series 11 (continued) type circuit remarks f ? n-ch open-drain output ? cmos input g ? lcdc output n-ch
mb89950 series 12 n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to pull-up or pull-down resistor. 3. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 4. power supply voltage fluctuations although operation is assured within the rated, rapid of v cc power supply voltage, a rapid fluctuation of the voltage cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc rippli fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 5. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
mb89950 series 13 n programming to the eprom on the mb89p955 the mb89p955 is an otprom version of the mb89950 series. 1. features ? 16-kbyte prom on chip ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in eprom mode is diagrammed below. 3. programming to the epprom functions equivalent to the mbm27c256a can be used in the mb89p955 eprom mode. accordingly, the user can write data with a general-purpose eprom writer by using a dedicated adapter. note that the electrical signature mode is not supported. ? programming procedure (1) set the eprom writer for the mbm27c256a. (2) load program data from 4000 h to 7fff h of the eprom writer (note that 0c000 h to 0ffff h in the operation mode are equivalent to 4000 h to 7fff h in the eprom mode). load option data from 3ff0 h to 3ff6 h of the eprom writer (see bit map on the next page for the correspondence to each option). (3) write the data with the eprom writer. 0000 h 0000 h not available prom 16 kb 0080 h 0280 h 8000 h bff0 h bff6 h ffff h c000 h 3ff0 h 3ff7 h 4000 h 7fff h eprom 16 kb vacancy (read value ff h ) option area vacancy (read value ff h ) single chip eprom mode (corresponding addresses on the eprom programmer) i/o ram not available option area not available address
mb89950 series 14 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield due to its nature, bit programming test cant be conducted as fujitsu delivery test. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel : (81)-3-3986-0403 fax : (81)-3-5396-9106 part number mb89p955pfm package qfp-64 compatible socket adapter sun hayato co., ltd. rom-64qf2-28dp-8l3 program, verify aging +150 c, 48 hrs. data verification assembly
mb89950 series 15 7. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map note: each bit is set to 1 as the initialized value, therefore the pull-up option is not selected. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3ff0 h vacancy readable and writable vacancy readable and writable vacancy readable and writable oscillation stabilization time 1: 2 18 /f c 0: 2 14 /f c reset pin ouput 1: yes 0: no power-on reset 1: yes 0: no vacancy readable and writable vacancy readable and writable 3ff1 h vacancy readable and writable p46 pull-up 1: yes 0: no p45 pull-up 1: yes 0: no p44 pull-up 1: yes 0: no p43 pull-up 1: yes 0: no p42 pull-up 1: yes 0: no p41 pull-up 1: yes 0: no p40 pull-up 1: yes 0: no 3ff2 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 3ff3 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 3ff4 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 3ff5 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable 3ff6 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable
mb89950 series 16 n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below: inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax : (81)-3-5396-9106 3. memory space memory space in each mode such as 32-kbyte prom, is diagrammed below. 4. programming to the eprom (1) set the eprom programmer for the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h . (3) program with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg prom 32 kb ffff h 0000 h 0080 h single chip i/o ram not available 7fff h 0000 h eprom 32 kb corresponding address on the eprom programmer address
mb89950 series 17 n block diagram n-ch open-drain i/o port port 2 and port 3 oscillator clock control reset circuit (wdt) 20-bit timebase timer 8-bit pwm timer r a m (256 8 bits) f 2 mc-8l cpu r o m (8 k 8 bits) other pins moda v cc , v ss p41/pwm x0 x1 internal bus bus 8-bit pulse width counter timer external interrupt p42/pwc/ int1 p45/sck p44/so p43/si rst noise clear 8-bit serial i/o uart cmos i/o port p40 p46/int0 n-ch open-drain i/o port port 0 and port1 lcd controller/driver 8 8 6 20 4 p00/seg20 to p07/seg27 p10/seg28 to p17/seg35 seg0 to seg19 com0 to com3 v3 p20/seg36 to p25/seg41 p33/v2 p32/v1 p30 p31 por t 4
mb89950 series 18 n cpu core 1. memory space f 2 mc-8l cpu has 64 kbytes of memory. all i/o, data program areas are located in this space. the i/o area is near the lowest address and the data area is immediately above it. the data area can be divided into register, stack, and direct-address areas according to the applications. the program area is located near the highest address, and the tables of interrupt and reset vectors and vector-call instructions are at the highest address in this area. the following figure shows the structure of the memory space for the mb89950 series of microcontrollers. ? memory space vacant register mb89953 rom i/o ram vacant register MB89951 rom i/o ram vacant register mb89pv950 rom i/o ram vacant register mb89p955 rom i/o ram reserved 0000 h 0080 h 0100 h 0140 h f000 h ffff h 00c0 h 0000 h 0080 h 0100 h 0180 h e000 h ffff h 0000 h 0080 h 0100 h 0280 h c000 h ffff h 0200 h 0000 h 0080 h 0100 h 0200 h 8000 h ffff h 0480 h
mb89950 series 19 2. registers the f 2 mc-8l family has two types of registers; dedicated hardware registers in the cpu and general-purpose memory registers. the following registers are provided: program counter (pc): a 16-bit register for indicating the instruction storage positions. accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which is used for arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit pointer for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1, 0 = 11 the other bit values are indeterminate. initial value ? structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
mb89950 series 20 the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to 0 otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes 1 as the result of an arithmetic operation. cleared to 0 when the bit is cleared to 0. z-flag: set to 1 when an arithmetic operation results in 0. cleared to 0 otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to 0 if the overflow does not occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
mb89950 series 21 the following general-purpose registers are provided: general-purpose registers: an 8-bit resister for storing data the general-purpose registers are of 8 bits and located in the register banks of the memory. one bank contains eight registers. up to a total of 4 banks can be used on the MB89951 and a total of 8 banks can be used on the mb89953 and a total of 16 banks can be used on the mb89p955 and a total of 32 banks can be used on the mb89pv950. the bank currently in use is indicated by the register bank pointer (rp). register bank configuration this address = 0100 h + 8 (rp) memory area 4 banks (MB89951) 8 banks (mb89953) 16 banks (mb89p955) 32 banks (mb89pv950) r0 r1 r2 r3 r4 r5 r6 r7
mb89950 series 22 n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h vacancy 02 h (r/w) pdr1 port 1 data register 03 h vacancy 04 h (r/w) pdr2 port 2 data register 05 h to 07 h vacancy 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbcr timebase timer control register 0b h vacancy 0c h (r/w) pdr3 port 3 data register 0d h vacancy 0e h (r/w) pdr4 port 4 data register 0f h (w) ddr4 port 4 data direction register 10 h vacancy 11 h 12 h (r/w) cntr pwm control register 13 h (w) comr pwm compare register 14 h (r/w) pcr1 pwc pulse width control register 1 15 h (r/w) pcr2 pwc pulse width control register 2 16 h (r/w) rlbr pwc reload buffer register 17 h (r/w) nccr pwc noise reduction control register 18 h to 1b h vacancy 1c h (r/w) smr serial mode register 1d h (r/w) sdr serial data register 1e h vacancy 1f h 20 h (r/w) smc1 uart serial mode control register 1 21 h (r/w) src uart serial rate control register 22 h (r/w) ssd uart serial status/data register 23 h (r/w) sidr/sodr uart serial data register 24 h (r/w) smc2 uart serial mode control register 2
mb89950 series 23 (continued) note: do not use vacancies. address read/write register name register description 25 h to 2f h vacancy 30 h (r/w) eic1 external interrupt 1 control register 1 31 h to 63 h vacancy 64 h to 78 h (r/w) vram display data ram 79 h (r/w) lcdr lcd control register 7a h (r/w) segr segment output select register 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h itr interrupt test register
mb89950 series 24 n electrical characteristics 1. absolute maximum ratings (v ss = 0.0 v) * : it is only suitable to mb89p955/pv950. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v lcd power supply voltage v3 v ss C 0.3 v ss + 7.0 v input voltage v i1 v ss C 0.3 v cc + 0.3 v all the pins must not exceed vss + 7.0 v, excluding p00 to p07, p10 to p17, p20 to p25,p32 to p33 in mb89p955/pv950 v i2 v ss C 0.3 v ss + 7.0 v applicable to p00 to p07, p10 to p17, p20 to p25 (port select) in MB89951/953 v i3 v ss C 0.3 v3 v *p00 to p07, p10 to p17, p20 to p25, p32 to p33 output voltage v o1 v ss C 0.3 v cc + 0.3 v all the pins must not exceed vss + 7.0 v, excluding p00 to p07, p10 to p17, p20 to p25, p32 to p33 in mb89p955/pv950 v o2 v ss C 0.3 v ss + 7.0 v applicable to p00 to p07, p10 to p17, p20 to p25 (port select) in MB89951/953 v o3 v ss C 0.3 v3 v p00 to p07, p10 to p17, p20 to p25, p32 to p33* l level output current i ol ? 10 ma applicable to all pins except power supply pin. l level average output current i olav ? 4ma applicable to all pins excluding power supply pin. specified as the average value in 1 hour. l level total output current ? i ol ? 40 ma h level output current i oh ? C5 ma applicable to all pins excluding power supply pin. h level average output current i ohav ? C2 ma applicable to all pins excluding power supply pin. specified as the average value in 1 hour. h level total output maximum current ? i oh ? C10 ma power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
mb89950 series 25 2. recommended operating conditions (v ss = 0.0 v) * : this value varies with the operating frequency and analog assurance range. see figure 1. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 2.2* 6.0 v usual operation guarantee range 1.5 6.0 v ram-data-holding guarantee range at stop mode lcd power supply voltage v3 v ss 6.0 v v3 pins for mb89953 the voltage range supplied to lcd and its optimum value depend on the lcd operating temperature t a C40 +85 c ? figure 1 operating voltage vs. main clock operating frequency (mhz) 1 2 3 4 5 operating frequency (mhz) 4.0 2.0 1.3 1.0 0.8 minimum instruction cycle ( m s) operating assurance range 6 5 4 3 2 1 operating voltage (v)
mb89950 series 26 3. dc characteristics (v cc = v3 = +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17, p20 to p25, p30 to p31, p40 to p46 0.7 v cc *1 0.3 v cc *1 v p32,p33 0.7 v cc *1 v3v v ihs rst , int0, sck, si, pwc/int1 0.8 v cc v cc + 0.3 v l level input voltage v il p00 to p07, p10 to p17, p20 to p25, p30 to p33, p40 to p46 v ss C 0.3 0.3 v cc *1 v v ils rst , moda, int0, sck, si, pwc/int1 v ss C 0.3 0.2 v cc v open-drain output pin applied voltage v d p30 to p31, p20 to p25, p10 to p17, p00 to p07 v ss C 0.3 v ss + 6.0 v p00 to p07, p10 to p17, p20 to p25 (port select) in MB89951/953 p32, p33 v ss C 0.3 v3 v p32 to p33 (port select) h level output voltage v oh p40 to p46 i oh = C2.0 ma 4.0 v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p25, p30 to p33 i ol = 4.0 ma 0.4 v v ol2 rst, p40 to p46 i ol = 4.0 ma 0.4 v input leakage current (hi-z output leak current) i li1 moda, p30, p31, p40 to p46 0.45 v < vi < v cc 5 m a when pull-up option is not selected p00 to p07, p10 to p17, p20 to p25, p32, p33 5 m a when pull-up option is not selected pull-up resistance r pull rst , p40 to p46 v i = 0.0 v 25 50 100 k w when pull-up option is selected common output impedance r vcom com0 to com3 v1 to v3 = +5.0 v 2.5k w
mb89950 series 27 (continued) (v cc = v3 = +5.0 v, v ss = 0.0 v, t a = C40 c to +85 c) *1: port input voltage is smaller than v3 for mb89p955/pv950. *2: tbd = to be determined *3: for information on t inst , see (4) instruction cycle in 4.ac characteristics. note: for pins for selection of segments (seg8 to seg31) and ports (p10 to p17, p40 to p47, p50 to p57), see the limits values of ports when port output is selected and those for segments when segment output is selected. parameter symbol pin name condition value unit remarks min. typ. max. segment output impedance r vseg seg0 to seg41 v1 to v3 = +5.0 v 15k w lcd divided resistance r lcd v1 to v3 30 60 120 k w lcd leak current i lcdl v1 to v3, com0 to com3, seg0 to seg41 10 m a pull-down resistance moda tbd tbd tbd k w power supply voltage i cc v cc f c = 5 mhz t inst *3 = 0.8 m s 3.55.0ma main run mode i ccs v cc fc = 5 mhz t inst *3 = 0.8 m s 1.11.7ma main sleep mode i cch v cc t a = +25 c0.11 m astop mode input capacitance c in except v cc and v ss f = 1 mhz 10 pf
mb89950 series 28 4. ac characteristics (1) reset timing (v cc = 5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) * : t xcyl is the oscillation cycle (1/f c ) to input to the xo pin. (2) specifications for power-on reset (v cc = 5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) note: if power-on reset provided is selected, an abrupt change in the power supply voltage could cause a power- on reset. when changing the power supply voltage during operation, voltage fluctuations should be two or less times for smooth start-up. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t xcyl *ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1ms min. interval time to the next power-on reset 0.2 v cc rst t zlzh v cc 0.2 v 2.0 v 0.2 v t r 0.2 v t off
mb89950 series 29 (3) clock timing (v ss = 0.0 v, t a = C40 c to +85 c) * : duty = p wh /t hcyl (4) instruction cycle (v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name value unit remarks min. typ. max. clock frequency f c x0, x1 1 5 mhz clock cycle time t hcyl x0, x1 400 2000 ns input clock duty ratio* duty x0 30 70 % crystal & ceramic input clock rising/falling time t cr t cf x0 10 ns applied when external clock used parameter symbol value unit remarks instruction cycle (minimum instruction executing time) t inst 4/f c to 64/f c m s t inst = 0.8 m s when operating at f c = 5 mhz ? timing conditions t cf t cr x0 0.8 v cc 0.2 v cc p wh when crystal or ceramic resonator is used open when external clock is used x0 x1 x0 x1 f c f ch c 0 c 1 0.8 v cc 0.8 v cc 0.2 v cc t hcyl p wl ? clock configurations
mb89950 series 30 (5) serial i/o & uart timing (v cc = 5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck internal clock operation 2 t inst * m s sck1 ? so time t slov sck, so 200 200 ns valid si ? sck - t ivsh si, sck 0.5 t inst * m s sck - ? valid si hold time t shix sck, si 0.5 t inst * m s serial clock h pulse width t shsl sck external clock operation 1 t inst * m s serial clock l pulse width t slsh sck 1 t inst m s sck1 ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 0.5 t inst * m s sck - ? valid si hold time t shix sck, si 0.5 t inst * m s
mb89950 series 31 ? internal shift clock mode ? external shift clock mode 0.8 v 2.4 v 0.8 v t slov 0.8 v 2.4 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ivsh t shix sck so si 0.7 v cc 0.2 v cc t slov 0.8 v 2.4 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ivsh t shix so si 0.2 v cc 0.7 v cc t slsh t shsl sck t scyc
mb89950 series 32 (6) peripheral input timing (v cc = 5.0 v 10%, v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name value unit remarks min. max. peripheral input h level pulse width 1 t ilih1 pwc, int1, int0 2 t inst * m s peripheral input l level pulse width 1 t ihil1 pwc, int1, int0 2 t inst * m s 0.2 v cc 0.2 v cc 0.8 v cc pwc, int, int0 0.8 v cc t ilih1 t ihil1
mb89950 series 33 n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
mb89950 series 34 table 2 transfer instructions (48 instructions) note during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
mb89950 series 35 table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
mb89950 series 36 (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
mb89950 series 37 n instruction map h l 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel
mb89950 series 38 n mask options *1: the main clock oscillation stabilization time is generated by dividing the main clock oscillation. since the oscillation cycle is unstable immedeately after oscillation starts, the time in this table is only a guide. *2: port/segment output switching should be specified in the same manner as the port allocation set by the segment output select register in the lcd controller/driver. *3: when those pins are used as ports, applied voltage should never be jogjer than v3. n ordering information no. model MB89951 mb89953 mb89p955 mb89pv950 specification method select when ordering mask set by eprom fixed 1 pull-up resistors p40 to p46 can be selected for each pin can be selected for each pin no pull-up resistor 2 port/segment output p00 to p07, p10 to p17, p20 to p25 can be selected for every 8 to 1 pins *2 port/segment output *3 port/segment output *3 3 power-on reset power-on reset available power-on reset unavailable selectable selectable power-on reset available 4 selection of main clock oscillation stabilization time (at 5 mhz) *1 approx. 2 18 /f c (approx. 52.4 ms) approx. 2 14 /f c (approx. 3.28 ms) selectable selectable 2 18 /f c 5 reset pin output reset output available reset output unavailable selectable selectable reset output available part number package remarks MB89951pfm mb89953pfm mb89p955pfm 64-pin plastic qfp (fpt-64p-m09) mb89pv950cf 64-pin ceramic mqfp (mqp-64c-m01)
mb89950 series 39 n package dimensions +0.20 C0.10 +.008 C.004 +0.05 C0.02 +.002 C.001 lead no. (stand off) 64 49 48 33 32 17 16 1 nom (.512) ref (.384) 13.00 9.75 (.012.004) 0.300.10 0.65(.0256)typ 12.000.10(.472.004)sq 14.000.20(.551.008)sq (.020.008) (.004.004) 0.100.10 0.500.20 0 10 details of "a" part "a" 1.50 .059 0.127 .005 1 pin index 0.10(.004) m 0.13(.005) 1994 fujitsu limited f64018s-1c-2 c (mounting height) +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.00(.472)typ (.039.010) 1.000.25 typ 18.00(.709) (.039.010) 1.000.25 (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 10.82(.426) (.006.002) 0.150.05 0.50(.020)typ 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m64004sc-1-3 c dimensions in mm (inches) dimensions in mm (inches) 64-pin plastic qfp (fpt-64p-m09) 64-pin ceramic mqfp (mqp-64c-p01)
mb89950 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, usa tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ f9609 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB89951

	To Download MB89951 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .